期刊
IEEE TRANSACTIONS ON ELECTRON DEVICES
卷 55, 期 1, 页码 163-174出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2007.911352
关键词
CMOS digital integrated circuits; leakage currents; logic design; low-power electronics; matching; static random access memory (SRAM); subthreshold; yield estimation
Minimum energy operation for digital circuits typically requires scaling the power supply below the device threshold voltage. Advanced technologies offer improved integration, performance, and active-energy efficiency for minimum energy sub-V-t circuits, but are plagued by increased variation and reduced I-ON/I-OFF ratios, which degrade the fundamental device characteristics critical to circuit operation by several orders of magnitude. This paper investigates those characteristics and presents design methodologies and circuit topologies to manage their severe degradation. The issues specific to both general logic and dense static random access memories are analyzed, and solutions that address their distinct design metries are presented.
作者
我是这篇论文的作者
点击您的名字以认领此论文并将其添加到您的个人资料中。
推荐
暂无数据