期刊
IEEE TRANSACTIONS ON ELECTRON DEVICES
卷 55, 期 1, 页码 8-20出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2007.911044
关键词
gate stack; hafnium oxides; high-k dielectric; metal electrode; scaling
High-k dielectrics have been intensively investigated during the last decade, and their performance as a gate dielectric has been improved to the level of conventional SiO2-based gate dielectric at an equivalent oxide thickness (EOT) similar to 1 nm. The understanding on metal electrodes and their interaction with the underlying high-k dielectric has been expanded, and various CMOS device results with metal electrode/high-k gate dielectric stacks have been reported, indicating the maturity of this technology. The next challenges lie in scaling the gate stack to 0.5-nm EOT to extend the usage of the metal electrode/high-k gate dielectric stacks to future technology generations. A new class of high-k dielectric that has a dielectric constant higher than 26 and a barrier height of similar to 5.0 eV and above will be needed to achieve this target. Recent progress in this so-called higher k dielectric research is summarized, and its benefit to the gate leakage current is discussed. This paper also reviews various extrinsic and intrinsic process-related defects in the deep subnanometer gate stacks and the potential challenges in implementing such a gate-stack system.
作者
我是这篇论文的作者
点击您的名字以认领此论文并将其添加到您的个人资料中。
推荐
暂无数据