Simulation Study of the Layout Technique for P-hit Single-Event Transient Mitigation via the Source Isolation

In this paper, a layout technique for P-hit single-event transient ( SET) mitigation via source isolation is studied by way of technology-computer-aided-design numerical simulations. The source-isolation layout design methodology is thoroughly discussed for the combinational standard cell. Based on a 90-nm twin-well CMOS technology, the simulation results indicate that the proposed radiation hardened by design (RHBD) technique can significantly reduce SET pulsewidth. The effects of the ion strike angles and strike locations on this hardened technique are also studied, and the area penalty is also discussed. When we combine the layout technique that utilizes the quenching effect with the proposed source-isolation layout technique, the RHBD standard-cell library can be further exploited for additional P-hit SET mitigation in the spaceborne integrated-circuit design.