期刊
IEEE TRANSACTIONS ON COMPUTERS
卷 60, 期 1, 页码 93-105出版社
IEEE COMPUTER SOC
DOI: 10.1109/TC.2010.202
关键词
Stochastic logic; reconfigurable hardware; fault-tolerant computation
资金
- Semiconductor Research Corporation's Focus Center Research Program [2003-NT-1107]
- US National Science Foundation (NSF) [0845650]
- Intel Corporation
Mounting concerns over variability, defects, and noise motivate a new approach for digital circuitry: stochastic logic, that is to say, logic that operates on probabilistic signals and so can cope with errors and uncertainty. Techniques for probabilistic analysis of circuits and systems are well established. We advocate a strategy for synthesis. In prior work, we described a methodology for synthesizing stochastic logic, that is to say logic that operates on probabilistic bit streams. In this paper, we apply the concept of stochastic logic to a reconfigurable architecture that implements processing operations on a datapath. We analyze cost as well as the sources of error: approximation, quantization, and random fluctuations. We study the effectiveness of the architecture on a collection of benchmarks for image processing. The stochastic architecture requires less area than conventional hardware implementations. Moreover, it is much more tolerant of soft errors (bit flips) than these deterministic implementations. This fault tolerance scales gracefully to very large numbers of errors.
作者
我是这篇论文的作者
点击您的名字以认领此论文并将其添加到您的个人资料中。
推荐
暂无数据