4.5 Article

Hydra: A Block-Mapped Parallel Flash Memory Solid-State Disk Architecture

期刊

IEEE TRANSACTIONS ON COMPUTERS
卷 59, 期 7, 页码 905-921

出版社

IEEE COMPUTER SOC
DOI: 10.1109/TC.2010.63

关键词

Flash memory; flash translation layer (FTL); solid-state disk (SSD); storage system

资金

  1. MEST/KOSEF [2009-0081569]
  2. National Research Foundation of Korea [2010-0015149, 2009-0081569] Funding Source: Korea Institute of Science & Technology Information (KISTI), National Science & Technology Information Service (NTIS)

向作者/读者索取更多资源

Flash memory solid-state disks (SSDs) are replacing hard disk drives (HDDs) in mobile computing systems because of their lower power consumption, faster random access, and greater shock resistance. We describe Hydra, a high-performance flash memory SSD architecture that translates the parallelism inherent in multiple flash memory chips into improved performance, by means of both bus-level and chip-level interleaving. Hydra has a prioritized structure of memory controllers, consisting of a single high-priority foreground unit, to deal with read requests, and multiple background units, all capable of autonomous execution of sequences of high-level flash memory operations. Hydra also employs an aggressive write buffering mechanism based on block mapping to ensure that multiple flash memory chips are used effectively, and also to expedite the processing of write requests. Performance evaluation of an FPGA implementation of the Hydra SSD architecture shows that its performance is more than 80 percent better than the best of the comparable HDDs and SSDs that we considered.

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