NEMS-Based Functional Unit Power-Gating: Design, Analysis, and Optimization

In order to combat the exponentially growing leakage power in modern microprocessors, researchers have proposed the use of alternative power-gating structures that can yield higher leakage savings with a much lower performance impact. A prime contender is an emerging CMOS-compatible power-gating device, the nanoelectromechanical systems (NEMS) switch. Compared to transistors, NEMS switches have zero off-state leakage, so for very long periods of sleep, their effectiveness is unparalleled. For systems with periods of faster on/off rates, however, their slower switching speed, high activation energy, and finite device lifetime become drawbacks. This motivates an exploration to determine whether NEMS switches are capable of fast, fine-grained power-gating. In this article, we provide an accurate energy model of functional-unit power-gating that allows us to effectively compare transistors and NEMS switches. It is also fast enough to support the optimization of a wide variety of circuit-and system-level parameters, including supply voltage, threshold voltage, and power-gating scheduler aggressiveness. Using this framework, we show that NEMS switch power-gates along with an ideal oracle power-gating policy can achieve an average 29.5% drop in total functional unit energy, compared to only 23.5% with transistor power-gates. A more realistic hardware-based policy for NEMS switches yields a 28.9% drop, compared to a 23.0% drop with transistors.