期刊
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
卷 57, 期 5, 页码 1048-1061出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCSI.2010.2046957
关键词
Full parallel; high throughput; low-density parity check (LDPC); low power; message passing; min sum; nanometer; 10GBASE-T; 65-nm CMOS; 802.3an
资金
- ST Microelectronics
- Intel Corporation
- UC Micro
- National Science Foundation [0430090, 0903549, 0546907]
- Semiconductor Research Corporation [1598, 1971, 1659]
- Intellasys Corporation
- SEM
- University of California at Davis (UCD) Faculty Research
- Direct For Computer & Info Scie & Enginr
- Division of Computing and Communication Foundations [0430090] Funding Source: National Science Foundation
- Direct For Computer & Info Scie & Enginr
- Division of Computing and Communication Foundations [0546907, 0903549] Funding Source: National Science Foundation
A low-complexity message-passing algorithm, called Split-Row Threshold, is used to implement low-density parity-check (LDPC) decoders with reduced layout routing congestion. Five LDPC decoders that are compatible with the 10GBASE-T standard are implemented using MinSum Normalized and MinSum Split-Row Threshold algorithms. All decoders are built using a standard cell design flow and include all steps through the generation of GDS II layout. An Spn = 16 decoder achieves improvements in area, throughput, and energy efficiency of 4.1 times, 3.3 times, and 4.8 times, respectively, compared to a MinSum Normalized implementation. Postlayout results show that a fully parallel Spn = 16 decoder in 65-nm CMOS operates at 195 MHz at 1.3 V with an average throughput of 92.8 Gbits/s with early termination enabled. Low-power operation at 0.7 V gives a worst case throughput of 6.5 Gbits/s-just above the 10GBASE-T requirement-and an estimated average power of 62 mW, resulting in 9.5 pJ/bit. At 0.7 V with early termination enabled, the throughput is 16.6 Gbits/s, and the energy is 3.7 pJ/bit, which is 5.8x lower than the previously reported lowest energy per bit. The decoder area is 4.84 mm(2) with a final postlayout area utilization of 97%.
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