期刊
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY
卷 20, 期 9, 页码 1260-1264出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCSVT.2010.2057017
关键词
Convolution interpolation; image reconstruction; scaling; very-large-scale integration (VLSI)
This letter presents a high-performance architecture of a novel first-order polynomial convolution interpolation for digital image scaling. A better quality of interpolation is achieved by using higher order model that requires complex computations. The kernel of the proposed method is built up of first-order poly-nomials and approximates the ideal sinc-function in the interval [-2, 2]. The proposed architecture reduces the computational complexity of generating weighting coefficients and provides a simple hardware architecture design and low computation cost, and easily meets real-time requirements. The architecture is implemented on the Virtex-II FPGA, and the high-performance very-large-scale integration architecture has been successfully designed and implemented with the TSMC 0.13 mu m standard cell library. The simulation results indicate that the interpolation quality of the proposed architecture is mostly better than cubic convolution interpolations, and is able to process varying-ratio image scaling for high-definition television in real-time.
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