期刊
IEEE JOURNAL OF SOLID-STATE CIRCUITS
卷 49, 期 3, 页码 708-717出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2014.2301769
关键词
Compact size; current-steering; DAC; DEM; digital return-to-zero; digital-to-analog converter; DRZ; dynamic element matching; figure-of-merit; FoM; high-resolution; high-speed; IMD; intermodulation distortion; mismatch insensitivity; return-to-zero; RTZ; SFDR; spurious-free dynamic range
资金
- National Science Council of Taiwan [NSC 102-2220-E-006-017]
For current-steering digital-to-analog converters (DACs), a technique utilizing dynamic-element-matching and digital return-to-zero, called DEMDRZ, is proposed to simultaneously suppress the mismatch-and transient-induced nonlinearity. In doing so, the usage of small-sized current sources and switches is possible, and the spurious-free dynamic range (SFDR) and intermodulation distortion (IMD) for high signal frequencies can be improved. With the DEMDRZ technique, a 12-bit compact, low-power, high-speed, high-resolution DAC is implemented in TSMC 40 nm CMOS process. The DAC architecture, circuit, and layout designs are presented. The implemented DAC achieves > 70 dB SFDR for signals over the 800 MHz Nyquist bandwidth at 1.6 GS/ s and < -61 dB IMD for signals over the 1.4 GHz Nyquist bandwidth at 2.8 GS/s. Further, it dissipates 40 mW with a single 1.2 V supply. The active area of the DAC is 0.016 mm(2), which is less than 6% of other state-of-the-art 12-bit current steering DACs. Furthermore, the implemented DAC performs best with three common figure-of-merits (FoMs).
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