期刊
IEEE JOURNAL OF SOLID-STATE CIRCUITS
卷 46, 期 9, 页码 2132-2147出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2011.2158024
关键词
CMOS sensor; image recognition; massive parallel; SIMD; vision chip
资金
- National Natural Science Foundation of China [60976023]
- Chinese National High-Tech Researching and Development Projection [2008AA010703]
- special funds for Major State Basic Research Project of China [2011CB932902]
This paper proposes a novel programmable vision chip based on multiple levels of parallel processors. The chip integrates CMOS image sensor, multiple-levels of SIMD parallel processors and an embedded microprocessor unit (MPU). The multiple-levels of SIMD parallel processors consist of an array processor of SIMD processing elements (PEs) and a column of SIMD row processors (RPs). The PE array and RPs have an O(N x N) parallelism and an O(N) parallelism, respectively. The PE array and RPs can be reconfigured to handle algorithms with different complexities and processing speeds. The PE array, RPs and MPU can execute low-, mid- and high-level image processing algorithms, respectively, which efficiently increases the performance of the vision chip. The vision chip can satisfy flexibly the needs of different vision applications such as image pre-processing, complicated feature extraction and over 1000 fps high-speed image capture. A prototype chip with 128 x 28 image sensor, 128 A/D converters, 32 8-bit RPs and 32 x 128 PEs is fabricated using the 0.18 mu m CMOS process. Applications including target tracking, pattern extraction and image recognition are demonstrated.
作者
我是这篇论文的作者
点击您的名字以认领此论文并将其添加到您的个人资料中。
推荐
暂无数据