A 2.1 M Pixels, 120 Frame/s CMOS Image Sensor With Column-Parallel Delta Sigma ADC Architecture

This paper presents a 2.1 M pixel, 120 frame/s CMOS image sensor with column-parallel delta-sigma (Delta Sigma)ADC architecture. The use of a second-order Delta Sigma ADC improves the conversion speed while reducing the random noise (RN) level as well. The Delta Sigma ADC employing an inverter-based Delta Sigma modulator and a compact decimation filter is accommodated within a fine pixel pitch of 2.25-mu m and improves energy efficiency while providing a high frame-rate of 120 frame/s. A prototype image sensor has been fabricated with a 0.13-mu m CMOS process. Measurement results show a RN of 2.4 e(rms)(-) and a dynamic range of 73 dB. The power consumption of the prototype image sensor is only 180 mW. This work achieves the energy efficiency of 1.7 e(-) .nJ.