期刊
IEEE JOURNAL OF SOLID-STATE CIRCUITS
卷 46, 期 12, 页码 2845-2856出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2011.2164302
关键词
Background calibration; current-steering; D/A converters; digital random return-to-zero (DRRZ); digital-analog conversion; digital-to-analog converter (DAC); return-to-zero (RZ)
资金
- National Science Council of Taiwan, R.O.C. [NSC-98-2221-E-009-131-MY2]
A current-steering digital-to-analog converter (DAC) was fabricated using a 90 nm CMOS technology. Its dynamic performance is enhanced by adopting a digital random return-to-zero (DRRZ) operation and a compact current cell design. The DRRZ also facilitates a current-cell background calibration technique that ensures the DAC static linearity. The measured differential nonlinearity (DNL) is 0.5 LSB and the integral nonlinearity (INL) is 1.2 LSB. At 1.25 GS/s sampling rate, the DAC achieves a spurious-free dynamic range (SFDR) better than 70 dB up to 500 MHz input frequency. The DAC occupies an active area of 1100 x 750 mu m(2). It consumes a total of 128 mW from a 1.2 V and a 2.5 V supply.
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