期刊
IEEE JOURNAL OF SOLID-STATE CIRCUITS
卷 45, 期 1, 页码 111-119出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2009.2034408
关键词
Through-silicon-via (TSV); via last; via middle; via first; three dimensional; 3-D architecture; stack; master; slave; DDR3 DRAM; double data rate; rank; module; connectivity check and repair; assembly yield; power noise reduction; refresh; power edge pads; seamless; gapless read
An 8 Gb 4-stack 3-D DDR3 DRAM with through-Si-via is presented which overcomes the limits of conventional modules. A master-slave architecture is proposed which decreases the standby and active power by 50 and 25%, respectively. It also increases the I/O speed to > 1600 Mb/s for 4 rank/module and 2 module/channel case since the master isolates all chip I/O loadings from the channel. Statistical analysis shows that the proposed TSV check and repair scheme can increase the assembly yield up to 98%. By providing extra VDD/VSS edge pads, power noise is reduced to < 100 mV even if all 4 ranks are refreshed every clock cycle consecutively.
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