期刊
IEEE JOURNAL OF SOLID-STATE CIRCUITS
卷 43, 期 9, 页码 1940-1950出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2008.2001912
关键词
CMOS readout; current steering circuit; high-speed imaging; H-tree clock distribution; integrated circuit design; snapshot exposures
A 64 x 64-pixel test circuit was designed and fabricated in 0.18-mu m CMOS technology for investigating high-speed imaging with large-format imagers. Several features are integrated into the circuit architecture to achieve fast exposure times with low-skew and jitter for simultaneous pixel snapshots. These features include an H-tree clock distribution with local and global repeaters, single-edge trigger propagation, local exposure control, and current-steering sampling circuits. To evaluate the circuit performance, test structures are periodically located throughout the 64 x 64-pixel device. Measured devices have exposure times that can be varied between 75 ps to 305 ps with skew times for all pixels less than +/- 3 ps and jitter that is less than +/- 1.2 ps rms. Other performance characteristics are a readout noise of approximately 115 e- rms and an upper dynamic range of 310,000 e-.
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