期刊
IEEE JOURNAL OF SOLID-STATE CIRCUITS
卷 43, 期 1, 页码 132-140出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2008.916028
关键词
NOR flash memory; DDR interface; multilevel flash
This paper describes a 1.8 V, 1 Gb 2 b/cell NOR Flash memory, based on time-domain voltage-ramp reading concept and designed in a 65 nm technology. Program method, architecture and algorithm to reach 2.25 MB/s programming throughput are also presented, as well as the read concept, allowing 70 ns random access time and a 400 MB/s sustained read throughput via a DDR interface.
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