期刊
IEEE JOURNAL OF SOLID-STATE CIRCUITS
卷 43, 期 2, 页码 342-350出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2007.914260
关键词
background calibration; capacitor mismatch and gain calibration; digital calibration; pipelined analog-to-digital converter; signal-dependent dithering
Pseudo-random dithers have been used to measure capacitor mismatch and opamp gain errors of the pipelined analog-to-digital converter (ADC) in background and to calibrate them digitally. However, this error measurement suffers from signal range reduction and long signal decorrelation time. A signal-dependent dithering scheme allows the injection of a large dither without sacrificing the signal range and shortens the signal decorrelation time. A 1.5-bit multiplying digital-to-analog converter (MDAC) stage is modified for signal-dependent dithering with two additional comparators, and its capacitor mismatch and gain errors are measured and calibrated as one error. When sampled at 20 MS/s, a 15-bit prototype ADC achieves a spurious-free dynamic range of 98 dB with 14.5-MHz input and a peak signal-to-noise plus distortion ratio of 73 dB with 1-MHz input. Integral nonlinearity is improved from 25 to 1.3 least significant bits (LSBs) after calibrating the first six stages. The chip is fabricated in 0.18-mu m CMOS process, occupies an active area of 2.3 x 1.7 mm(2), and consumes 285 mW at 1.8 V.
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