期刊
IEEE ELECTRON DEVICE LETTERS
卷 35, 期 1, 页码 141-143出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2013.2290555
关键词
Silicon nanowire; reconfigurable transistor; RFET; inverter; logic gates; transient simulations
资金
- Deutsche Forschungsgemeinschaft in the framework of the Project ReproNano [MI 1247/6-1]
- Cluster of Excellence CfAED
A feasibility and performance study of electrically reconfigurable nanowire transistors with selectable pFET and nFET operations is presented. The challenges toward circuit implementation are evaluated based on transient simulations of logic circuits. A novel physical structure capable of computing a NAND as well as NOR function is introduced. The new approach provides a flexible platform to develop and test fine-grain reconfigurable circuits and systems.
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