Enhanced Electrostatic Integrity of Short-Channel Junctionless Transistor With High-κ Spacers

We propose the use of a high-kappa spacer to improve the electrostatic integrity and, thereby, the scalability of silicon junctionless transistors (JLTs) for the first time. Using extensive simulations of n-channel JLTs, we demonstrate that the high-kappa spacers improve the electrostatic integrity of JLTs at sub-22-nm gate lengths. Electric field that fringes through the high-kappa spacer to the device layer on either sides of the gate results in an effective increase in electrical gate length in the OFF-state. However, the effective gate length is unaffected in the ON-state. Hence, the OFF-state leakage current is reduced by several orders of magnitude with the use of a high-kappa spacer with concomitent improvements in the subthreshold swing and drain-induced barrier lowering. A marginal improvement in the ON-state current is observed with the use of the high-kappa spacer, and this is related to the reduction in parasitic resistance in the silicon under the spacer due to fringe fields.