期刊
IEEE ELECTRON DEVICE LETTERS
卷 32, 期 6, 页码 728-730出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2011.2131111
关键词
CMOS inverter; dopant segregation (DS); MOSFETs; Schottky barrier (SB); silicon-on-insulator (SOI)
资金
- European Commission [016677, 216171]
This letter demonstrates the integration of complementary dopant-segregated Schottky barrier MOSFETs into CMOS inverters. The implementation of a valence-band-edge silicide, namely, PtSi, associated to arsenic (As) and boron (B) low-temperature segregation is validated for the first time at the circuit level. Current drives for n- and p-type devices are I-on = 596/378 mu A/mu m at V-ds = vertical bar 1.1 V vertical bar and vertical bar V-gs vertical bar = 2 V to account for the 2.4-nm gate oxide thickness. Excellent inverter voltage transfer characteristics, large voltage gain, and appreciable noise margins have been obtained down to 0.5 V of supply voltage.
作者
我是这篇论文的作者
点击您的名字以认领此论文并将其添加到您的个人资料中。
推荐
暂无数据