Two-pulse C-V: A new method for characterizing electron traps in the bulk of SiO2/high-k dielectric stacks

SiO2/high-k, dielectric stack is a candidate for replacing the conventional SiO2-based dielectric stacks for future Flash memory cells. Electron traps in the high-k layer can limit the memory retention via the trap-assisted tunneling, and there is a pressing need for their characterization. A new two-pulse C-V measurement technique is developed in this letter, which, for the first time, allows us to probe the discharge of electron traps throughout the SiO2/high-k stack. It complements the charge pumping technique, which can only probe near-interface traps. It is demonstrated that a large number of electron traps, indeed, exist in the bulk of high-k layer. Bulk electron traps also have different discharge characteristics from those near the SiO2/high-k interface.