Journal
ELECTRONICS LETTERS
Volume 49, Issue 21, Pages -Publisher
INST ENGINEERING TECHNOLOGY-IET
DOI: 10.1049/el.2013.2479
Keywords
circuit complexity; demodulators; frequency shift keying; radiocommunication; bit rate 5 Mbit; s; digital data transmission chain; circuit complexity; demodulator design; wireless communication; high-date-rate FSK demodulator
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Funding
- Innovation and Technology Commission (ITC), HKSAR [ITS/459/09FP]
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A low-power frequency-shift keying (FSK) demodulator capable of demodulating 5 Mbit/s data rate is presented. No high sampling clock is needed in this demodulator design, and thus the design not only greatly reduces the circuit complexity but also achieves a high data rate. It is suitable for a digital data transmission chain of wireless communication.
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