Journal
CIRP ANNALS-MANUFACTURING TECHNOLOGY
Volume 62, Issue 1, Pages 307-310Publisher
ELSEVIER
DOI: 10.1016/j.cirp.2013.03.069
Keywords
Defect; Polishing; Semiconductor
Funding
- Samsung Electronics Company, Ltd.
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In the chemical-mechanical polishing (CMP) of semiconductor structures, such defects as micro- and nano-scale scratches are frequently produced on the surfaces being polished. Recent research shows that not only agglomerated abrasives but the softer pad asperities in frictional contact also scratch the relatively hard surfaces. Accordingly, pad scratching is modeled based on the topography and mechanical properties of pad asperities. Asperity radius, R-a, and the standard deviation of asperity heights, sigma(z), are identified as the key topographical parameters. The theoretical models and experimental results show that pad scratching in CMP can be mitigated by increasing R-a/sigma(z). (C) 2013 CIRP.
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