Journal
VLSI DESIGN
Volume 11, Issue 3, Pages 285-300Publisher
HINDAWI LTD
DOI: 10.1155/2000/19436
Keywords
circuit partitioning; physical design; placement; multilevel
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In this paper, we present a new multilevel k-way hypergraph partitioning algorithm that substantially outperforms the existing state-of-the-art K-PM/LR algorithm for multiway partitioning, both for optimizing local as well as global objectives. Experiments on the ISPD98 benchmark suite show that the partitionings produced by our scheme are on the average 15% to 23% better than those produced by the K-PM/LR algorithm, both in terms of the hyperedge cut as well as the (K - 1) metric. Furthermore, our algorithm is significantly faster, requiring 4 to 5 times less time than that required by K-PM/LR.
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