Journal
IEEE ELECTRON DEVICE LETTERS
Volume 22, Issue 1, Pages 35-37Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/55.892436
Keywords
capacitance; effective oxide thickness; gate dielectric; inversion quantization; MOS devices; polysilicon depletion
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We have systematically compared the results of an extensive ensemble of the most advanced available quantum-mechanical capacitance-voltage (C-V) simulation and analysis packages for a range of metal-oxide-semiconductor device parameters. While all have similar trends accounting for polysilicon depletion and quantum-mechanical confinement, quantitatively, there is a difference of up to 20 % in the calculated accumulation capacitance for devices with ultrathin gate dielectrics. This discrepancy leads to large inaccuracies in the values of dielectric thickness extracted from capacitance measurements and illustrates the importance of consistency during C-V analysis and the need to fully report how such analysis is done.
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