Threshold voltage mismatch and intra-die leakage current in digital CMOS circuits

Due to device and voltage scaling scenarios for present and future deep-submicron CMOS technologies, it is inevitable that the off-state current (I-off) of MOSFET transistors increases as the technology minimum dimensions scale down. Experimental evidence shows that the leakage current distribution of modern, deep-submicron designs not only has a higher mean value but it also presents a larger variability as well. In this paper, we investigate the impact of threshold voltage mismatch as one plausible source for this increased variability. In digital circuit design, it is commonly assumed that the threshold voltage difference (mismatch) of static CMOS cells is negligible. However, threshold voltage mismatch (DeltaV(to)) has a two-sided effect on the oft-state current. Namely, the total cell's current can increase or decrease depending upon the direction of the V-t mismatch shift. This effect can be so severe that I-off can increase by more than one order of. magnitude with, respect to its nominal value due only to V-to mismatch. We further show through experimental results that the V-to mismatch of paired transistors working in the subthreshold regime can be worse by a factor of two as compared to transistors working in the saturation or linear regions. A factor of two larger spread is obviously quite devastating in terms of area, speed, and power consumption, should it be desired to attain the same I-off level as for a V-to mismatch characterized out of the subthreshold regime.