Impact of AlN Spacer on Analog Performance of Lattice-Matched AlInN/AlN/GaN MOSHEMT

In this work, a detailed investigation of the impact of spacer layer thickness on analog performance of an AlInN/AlN/GaN metal oxide semiconductor high electron mobility transistor (MOSHEMT) is carried out. A thorough analysis of the key figure-of-merits such as threshold voltage (V (th)), two-dimensional electron gas sheet charge density (n (s)), drain current (I (d)), transconductance (g (m)), and gate leakage current are performed for various spacer thicknesses ranging from 0.5 nm to 1.8 nm. From the two-dimensional ATLAS device simulation results, it is observed that the performance of AlInN/AlN/GaN MOSHEMT is affected by the variation of spacer thickness. Also, we have developed mathematical expressions for the evaluation of V (th) , n (s) , I (d) , g (m) and gate leakage current for the proposed device. The model results and technology computer-aided design simulation results are verified and also found to be satisfactory. Improved sheet charge density and superior analog performance is observed due to the insertion of the AlN spacer. Suppression in the forward gate current is observed due to the insertion of the AlN spacer which made it possible to apply a high gate voltage in the transistor operation. From the fabrication point of view, it is also feasible to utilize the existing complementary metal-oxide-semiconductor process flows to fabricate the proposed device.