Journal
IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume 54, Issue 1, Pages 106-114Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2006.887226
Keywords
gate leakage; gate stacks; high-kappa dielectric materials; tunneling
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In this paper, we compare the capacitance-voltage and current-voltage characteristics of gate stacks calculated with different simulation models developed by seven different research groups, including open and closed boundaries approaches to solve the Schrodinger equation inside the stack. The comparison has been carried out on template device structures, including pure SiO2 dielectrics and high-kappa, stacks, forcing the use of the same physical parameters in all models. Although the models are based on different modeling assumptions, the discrepancies among results in terms of capacitance and leakage current are small. These discrepancies have been carefully investigated by analyzing the individual modeling parameters and the internal quantities (e.g., tunneling probabilities and subband energies) contributing to current and capacitance.
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