Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 42, Issue 6, Pages 1196-1205Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2007.897157
Keywords
ADC; analog-to-digital conversion; circuit noise; CMOS analog integrated circuits; low-power electronics; offset compensation; scaleable; successive approximation register
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A resolution-rate scalable ADC for micro-sensor networks is described. Based on the successive approximation register (SAR) architecture, this ADC has two resolution modes: 12 bit and 8 bit, and its sampling rate is scalable, at a constant figure-of-merit, from 0-100 kS/s and 0-200 kS/s, respectively. At the highest performance point (i.e., 12 bit, 100 kS/s), the entire ADC (including digital, analog, and reference power) consumes 25 mu W from a 1-V supply. The ADC's CMRR is enhanced by common-mode independent sampling and passive auto-zero reference generation. The efficiency of the comparator is improved by an analog offset calibrating latch, and the preamplifier settling time is relaxed by self timing the bit-decisions. Prototyped in a 0.18-mu m, 5M2P? CMOS process, the ADC, at 12 bit, 100 kS/s, achieves a Nyquist SNDR of 65 dB (10.55 ENOB) and an SFDR of 71 dB. Its INL and DNL are 0.68 LSB and 0.66 LSB, respectively.
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