Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 35, Issue 2, Pages 240-247Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/4.823449
Keywords
delay-locked loop; time of flight; time-to-digital converter; Vernier delay line
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This paper describes a CMOS time-to-digital converter (TDC) integrated circuit utilizing tapped delay lines. A technique that allows the achievement of high resolution with low dead-time is presented. The technique is based on a Vernier delay line (VDL) used in conjunction with an asynchronous read-out circuitry. A delay-locked loop (DLL) is used to stabilize the resolution against process variations and ambient conditions. A test circuit fabricated in a standard 0.7-mu m digital CMOS process is presented, The TDC contains 128 delay stages and achieves 30-ps resolution, stabilized by the DLL, with the accuracy exceeding +/-1 LSB. Test results show that even higher resolutions can be achieved using the VDL method, and resolutions down to 5 ps are demonstrated to be obtainable.
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