Journal
IEEE ELECTRON DEVICE LETTERS
Volume 21, Issue 4, Pages 173-175Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/55.830972
Keywords
hard mask; metallurgical length; NMOSFET; pockets; tunneling dielectric; 20-nm gate length
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We have demonstrated the feasibility of 20-nm gate length NMOSFET's using a two-step hard-mask etching technique. The gate oxide is 1.2-nm thick, We have achieved devices with real N- arsenic implanted extensions and BF2 pockets. The devices operate reasonably well down to 20-nm physical gate length, These devices are the shortest devices ever reported using a conventional architecture.
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