Journal
IEEE TRANSACTIONS ON NUCLEAR SCIENCE
Volume 47, Issue 6, Pages 2603-2608Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/23.903815
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A new cell design technique is described which may be used to create SEU hardened circuits. The technique uses actively biased, isolated well transistors to prevent transients in combinational logic from reaching the output node.
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