Journal
IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY
Volume 11, Issue 1, Pages 533-536Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/77.919400
Keywords
Josephson junction; random access memory; single flux quantum device; latching device
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We have developed a 256-bit superconducting latching/SFQ hybrid (SLASH) RAM block as the first step in developing a 16-Kbit SLASH RAM, which enables high-frequency clock operation up to 10 GHz The SLASH RAM is composed of ac-powered latching devices and de-powered SFQ devices. The 256-bit SLASH RAM block is composed of 16x16 matrix array of vortex transitional memory cells, SFQ-NOR decoders, latching drivers, latching sense circuits, and address buffers. The 256-bit SLASH RAM block chips were fabricated and tested. We confirmed that the 256-bit SLASH RAM block functioned successfully.
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