Journal
IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume 48, Issue 4, Pages 701-706Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/16.915695
Keywords
grain boundaries; modeling; polycrystalline silicon; thin-film transistors
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Large-grain excimer laser-annealed polysilicon TFTs are studied. Due to the large grain size of the polysilicon film (about 2.5 mum), we propose a model for the on-current (above threshold voltage) taking into account the number of grain boundaries within the channel. This linear-region model considers grain and grain boundaries as two noncorrelated regions within the channel of a polysilicon TFT. The trap density at the grain boundaries and the device parameters involved in this model are determined by fitting the experimental transfer characteristic in the linear regime. Moreover, we show that the proposed model provides reliable results within a temperature range from 150 K to 300 K, Finally, it serves to optimize the energy density of laser annealing and to make predictions about polysilicon TFT technology, since TFTs performances versus grain size plots can be obtained.
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