Journal
IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume 48, Issue 4, Pages 696-700Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/16.915694
Keywords
charge-trap memory; Ge nano-crystal
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In this work, we describe a novel technique of fabricating germanium nanocrystal quasinonvolatile memory device. The device consists of a metal-oxide-semiconductor field-effect transistor (MOSFET) with Ge charge-traps embedded within the gate dielectric. The trap formation method provides for precise control of the thicknesses of the top (control) and bottom (tunneling) oxide layers which sandwich the charge-traps, via thermal oxidation. This memory device exhibits write/erase speed/voltage and retention time superior to previously reported nano-crystal or charge-trap memory devices, A detailed description of the novel process for fabricating the Ge charge-trap MOS memory is given, along with the resultant memory-cell performance characteristics.
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