Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 36, Issue 4, Pages 706-711Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/4.913751
Keywords
back-plane drivers; CMOS integrated circuits; high-speed integrated circuits; input/output (I/O); low-power design; low-voltage differential signaling (LVDS)
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This paper presents the design and the implementation of input/output (I/O) interface circuits for Gb/s-per-pin operation, fully compatible with low-voltage differential signaling (LVDS) standard. Due to the differential transmission technique and the low voltage swing, LVDS allows high transmission speeds and low power consumption at the same time, In the proposed transmitter, the required tolerance on the de output levels was achieved over process, temperature, and supply voltage variations with neither external components nor trimming procedures, by means of a closed-loop control circuit and an internal voltage reference. The proposed receiver implements a dual-gain-stage folded-cascode architecture which allows a 1.2-Gb/s transmission speed with the minimum common-mode and differential voltage at the input, The circuits were implemented in a 3.3-V 0.35-mum CMOS technology in a couple of test chips, Transmission operations up to 1.2 Gb/s with random data patterns and up to 2 Gb/s in asynchronous mode were demonstrated. The transmitter and receiver pad cells exhibit a power consumption of 43 and 33 mW, respectively.
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