Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 36, Issue 7, Pages 1138-1143Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/4.933473
Keywords
CMOS; low power; SC technique; self-timed comparator
Categories
Ask authors/readers for more resources
Based on a conventional successive approximation ADC architecture a new and faster solution is presented. The input structure of the new solution consists of transmission gates and capacitors only and there is no need for any active element. h switching circuit is implemented to allow a wider input voltage range of the ADC, Together with a self-timed comparator the power consumption is noticeably reduced while at the same time the sampling rate is doubled. Smaller input and reference capacitances reduce the requirements on the input and reference sources, respectively, Additionally, a widely clock-duty-cycle-independent control logic improves the applicability of the converter cell, especially for systems on chip. Results of measurements confirm the theoretical improvements.
Authors
I am an author on this paper
Click your name to claim this paper and add it to your profile.
Reviews
Recommended
No Data Available