4.5 Article

A fast high-resolution track trigger for the H1 experiment

Journal

IEEE TRANSACTIONS ON NUCLEAR SCIENCE
Volume 48, Issue 4, Pages 1276-1281

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/23.958765

Keywords

content addressable memory (CAM); digital signal processor (DSP); fast track trigger (FTT); field-programmable gate array (FPGA); H1 collaboration; HERA collider; track trigger; trigger

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After 2001, the upgraded ep collider HERA will provide an about five times higher luminosity for the two experiments Hl and ZEUS. To cope with the expected higher event rates, the Hl collaboration is building a track-based trigger system, the Fast Track Trigger (FTT). It will be integrated in the first three levels (L1-L3) of the HI trigger scheme to provide higher selectivity for events with charged particles. The FTT will allow reconstruction of three-dimensional tracks in the central drift chamber down to 100 MeV/c within the L2 latency of similar to 23 mus. To reach the necessary momentum resolution of,similar to5% (at 1 GeV/c), sophisticated reconstruction algorithms have to be implemented using high-density field-programmable gate arrays and their embedded content addressable memories. The final track parameter optimization will be done using noniterative fits implemented in digital signal processors. While at the first trigger level rough track information will be provided, at L2 tracks with high resolution are available to form trigger decisions on topological and other track-based criteria like multiplicities and momenta. At the third trigger level, a farm of commercial processor boards will be used to compute physics quantities such as invariant masses.

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