Design of low-noise transimpedance amplifiers with capacitive feedback

This paper reports on a new topology and design methodology for ultra-low noise and high-gain transimpedance amplifiers. This paper also reports on measurement results of two implemented ICs based on the proposed topology and fabricated in 130 nm IBM and 180 nm TSMC technologies. A capacitive feedback topology is implemented as a noise-efficient feedback network, analytical noise calculations in this family of TIA circuits are presented, and optimum noise criterion is derived. The saturation and instability problem of TIA circuits resulted from DC dark current of the input photodiodes is also addressed and a simple yet efficient feedback solution is proposed. The measurement results of 130 nm chip show average input referred noise of 2.67 pA/aeHz with bandwidth of 81 kHz to 1.76 GHz and transimpedance gain of 76 dBabroken vertical bar while dissipating 13.7 mW from a 1.5 V power supply, including the output buffer. The measurement results of 180 nm chip show average input referred noise of 3.18 pA/aeHz with bandwidth of 72 kHz to 1.62 GHz and transimpedance gain of 75 dBabroken vertical bar while dissipating 26.3 mW from a 2.2 V power supply, including the output buffer.