A digitally self-calibrating 14-bit 10-MHz CMOS pipelined A/D converter

A digitally self-calibrating pipelined analog-to-digital converter (ADC) featuring 1.5-bit/stage structure is presented. The integral (INL) and differential nonlinearity (DNL) errors are removed using a novel digital calibration algorithm, which also eliminates missing codes that can occur with other calibration algorithms near the extremes of the input range. After calibration, the measured DN-L is +/-0.6 LSB and the INL is +/-2.5 LSB at the 14-bit level. Sampling at a 10-MHz rate, the chip dissipates 220 mW and (post-cafibration) yields a signal-to-noise ratio of 77 dB and a spurious-free dynamic range of 95 dB with 4.8-MHz sine wave input signal. The chip is fabricated in 0.5-mum CMOS double-poly double-metal process, measures 3.8 mm x 3.3 mm (150 mil x 130 mil), and operates from a single 5-V supply.