Modeling double-layer capacitor behavior using ladder circuits

The double-layer capacitor (DLC) is a very complex device that is best represented by a distributed parameter system. Many different lumped-parameter equivalent circuits have been proposed for the DLC. An examination into utilizing a ladder circuit to model a DLC is presented. Parameters for different ladder circuits are determined from ac impedance data. Variations in circuit parameters with dc bias and manufacturing have been investigated. The performance of the ladder circuit has been evaluated in slow discharge and pulse load applications.