Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 38, Issue 7, Pages 1261-1265Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2003.813217
Keywords
analog-to-digital converters (ADCs); CMOS analog integrated circuits; low-power; low supply voltage; successive approximation; switched-capacitor circuits
Categories
Ask authors/readers for more resources
A successive approximation analog-to-digital converter (ADC) is presented operating at ultralow supply voltages. The circuit is realized in a 0.18-mum standard CMOS technology. Neither low-V-T devices nor voltage boosting techniques are used. All voltage levels are between supply voltage V-DD and ground V-SS. A passive sample-and-hold stage and a capacitor-based digital-to-analog converter are used to avoid application of operational amplifiers, since opamp operation requires higher values for the lowest possible supply voltage. The ADC has signal-to-noise-and-distortion ratios of 51.2 and 43.3 dB for supply voltages of 1 and 0.5 V, at sampling rates of 150 and 4.1 kS/s and power consumptions of 30 and 0.85 muW, respectively. Proper operation is achieved down to a supply voltage of 0.4 V.
Authors
I am an author on this paper
Click your name to claim this paper and add it to your profile.
Reviews
Recommended
No Data Available