Journal
IEEE TRANSACTIONS ON AUTOMATIC CONTROL
Volume 49, Issue 5, Pages 850-855Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TAC.2004.828312
Keywords
digital redesign; sampled-data control systems; uniform-in-time convergence
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This note proposes sufficient conditions that guarantee uniform-in-time convergence, as the sampling period approaches zero, of the control input to and the controlled output of a plant under sampled-data control to those corresponding signals of the same plant under continuous-time control. Sampled-data control systems exhibiting such behavior are formally defined as sampled-data models, which can be very convenient in the analysis and design of sampled-data systems since they can warn the engineer if a known limiting closed-loop behavior is likely to be violated. This practical consideration often occurs in digital redesign, where an analog control law is implemented digitally, with the objective of preventing intersample ripples.
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