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JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS
Volume 43, Issue 9A, Pages 6032-6037Publisher
JAPAN SOC APPLIED PHYSICS
DOI: 10.1143/JJAP.43.6032
Keywords
spintronics; spin transistor; spin MOSFET; reconfigurable logic; FPGA
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We propose and numerically simulate novel reconfigurable logic gates employing spin metal-oxide-semiconductor field-effect transistors (spin MOSFETs). The output characteristics of the spin MOSFETs depend on the relative magnetization configuration of the ferromagnetic contacts for the source and drain, that is, high current-drive capability in parallel magnetization and low current-drive capability in antiparallel magnetization [S. Sugahara and M. Tanaka: Appl. Phys. Lett. 84 (2004) 2307]. A reconfigurable NAND/NOR logic gate can be realized by using a spin MOSFET as a driver or an active load of a complimentary MOS (CMOS) inverter with a neuron MOS input stage. Its logic function can be switched by changing the relative magnetization configuration of the ferromagnetic source and drain of the spin MOSFET. A reconfigurable logic gate for all symmetric Boolean functions can be configured using only five CMOS inverters including four spin MOSFETs. The operation of these reconfigurable logic gates was confirmed by numerical simulations using a simple device model for the spin MOSFETs.
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