Timing vulnerability factors of sequentials

Single-event upsets (SEUs) from particle strikes have become a key challenge in microprocessor design. Modern superpipelined microprocessors typically contain many thousands of sequentials whose soft-error rate (SER) cannot be neglected anymore. An accurate assessment of the SER of sequentials is therefore crucial. This paper describes a method for computing timing vulnerability factors (TVFs) of sequentials. Our methology captures the impact of the circuit environment which sequentials are typically placed in. Further, upsets occurring in local clock nodes have been accounted for. Results are presented for master-slave type flip flops and for flow-through latches of a high-performance microprocessor. Our investigations demonstrate that TVFs are a strong function of the propagation delay of the combinational logic and typically vary between similar to0% and 50%. For high-performance microprocessors, we predict average TVF values of the order of 20%-30%. Further, we expect TVFs; to be largely technology independent for the same design.