4.6 Article

A self-aligned process for high-voltage, short-channel vertical DMOSFETs in 4H-SiC

Journal

IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume 51, Issue 10, Pages 1721-1725

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2004.835622

Keywords

counter-doping; DMOS; high-voltage MOSFET; nitric oxide (NO) anneal; self-aligned; short-channel; SiC

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In this paper, we describe a self-aligned process to produce short-channel vertical power DMOSFETs in 4H-SiC. By reducing the channel length to less than or equal to0.5 mum, the specific on-resistance of the MOSFET channel is proportionally reduced, significantly enhancing performance.

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