Design techniques for a pipelined ADC without using a front-end sample-and-hold amplifier

Design techniques for a low-power pipelined analog-to-digital converters (ADCs) without using a front-end sample-and-hold amplifier are presented. Two sampling topologies are compared that minimize aperture error by matching the time constant between signal paths. A digital correction expansion technique is also presented for multibit ADCs, which further increases tolerance to aperture error. Elimination of the front-end SHA can save more than half of the ADCs static power dissipation.