Journal
APPLIED PHYSICS LETTERS
Volume 99, Issue 26, Pages -Publisher
AMER INST PHYSICS
DOI: 10.1063/1.3669536
Keywords
adders; CMOS logic circuits; elemental semiconductors; logic gates; rectification; silicon; single electron transistors; ternary logic
Categories
Funding
- European Community (EC)
- Future Emerging Technology (FET)
- Molecular Logic Circuits (MOLOC) [215750]
- Atom Functionalities on Silicon Devices (AFSID) [214989]
- Australian Research Council Centre of Excellence for Quantum Computation and Communication Technology [CE110001027]
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Ternary logic has the lowest cost of complexity, here, we demonstrate a CMOS hardware implementation of a ternary adder using a silicon metal-on-insulator single electron transistor. Gate dependent rectifying behavior of a single electron transistor (SET) results in a robust three-valued output as a function of the potential of the single electron transistor island. Mapping logical, ternary inputs to the three gates controlling the potential of the single electron transistor island allows us to perform complex, inherently ternary operations, on a single transistor. (C) 2011 American Institute of Physics.[doi: 10.1063/1.3669536]
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