An electrical evaluation method for the silicidation of silicon nanowires

Physical and electrical properties of PtSi nanowires (NWs) fabricated on a silicon-on-insulator wafer are investigated. The Si consumption rule in NW silicidation is consistent with that of planar process. The cross-sectional area ratio between PtSi NW and Si NW is about 1.5:1. An electrical method is used to evaluate the silicidation degree of NWs. According to the dependence of the current passing through the NW on the backside substrate voltage, we can determine whether the Si NW is fully or partially silicided. The electrical evaluation results are in agreement with transmission electron microscopy inspections.