4.4 Article

Ultrashort SONOS memories

Journal

IEEE TRANSACTIONS ON NANOTECHNOLOGY
Volume 3, Issue 4, Pages 417-424

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TNANO.2004.834161

Keywords

CMOS device scaling; nonvolatile memory; scaling limits; silicon-on-insulator (SOI) technology; silicon-oxide-nitride-oxide-silicon (SONOS) memory

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We report the operational characteristics, of ultrashort SONOS memories down to similar to30-nm effective gate length. Good sub-threshold swing, good drain-induced barrier lowering (similar to120 mV/decade), and similar to2.4 V of memory window down to the smallest dimensions demonstrate the improvements that result from a thin tunneling oxide and a large trapping center density. The use of distributed defects and thin tunneling oxide is reflected in a memory window that is stable up to at least 10(5) cycles for the smallest devices. The smallest structures tested employ similar to75 electrons for memory storage, which allows for device to device reproducibility. The capture and emission processes asymmetries point to the differences in the energy parameters of the two processes. The smallest structures, however, do show loss of retention time compared to the larger structures, for the same oxide-nitride-oxide stack thickness, and this is believed to arise from higher leakage due to higher defects distribution in the gate insulators from process-induced damage. All tested devices, down to similar to30-nm effective gate length, show very good endurance characteristics.

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