Journal
APPLIED PHYSICS EXPRESS
Volume 4, Issue 5, Pages -Publisher
JAPAN SOC APPLIED PHYSICS
DOI: 10.1143/APEX.4.051301
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Funding
- Ministry of Education, Culture, Sports, Science and Technology, Japan [21246054]
- Grants-in-Aid for Scientific Research [23760017, 21246054] Funding Source: KAKEN
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We fabricated Ge n- and p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with (100) surface orientation by the gate-last process. The source/drain junctions for n- and p-MOSFETs were fabricated by thermal diffusion of P and ion implantation of B, respectively, which indicated high on/off ratios. An ultrathin SiO2/GeO2 interlayer was used for fabricating the gate stack. The fabricated MOSFETs showed excellent electrical characteristics with a low interface state density. The peak electron and hole mobilities were 1097 and 376 cm(2) V-1 s(-1), respectively, despite the very thin GeO2 thickness (2 nm). These are 1.5-1.6 times higher than those of Si MOSFETs. (C) 2011 The Japan Society of Applied Physics
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